View MAX32626IWY_9007618.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the max32625/max32626 is an arm ? cortex ? -m4f 32-bit microcontroller with an unconnected point unit, ideal for the emerging category of wearable medical and fitness applications. the architecture combines ultra- low power, high-efficiency signal processing functionality and ease of use. an internal 96mhz oscillator provides high-performance capability, and the internal 4mhz oscil - lator supports minimal power consumption for applica - tions requiring always-on monitoring. the device provides 512kb of flash and 160kb of sram. the device features four powerful and flexible power modes. a peripheral management unit (pmu) enables intelligent peripheral control with up to six channels to significantly reduce power consumption. built-in dynamic clock gating and firmware-controlled power gating allows the user to optimize power for the specific application. multiple spi, uart, and i 2 c serial interfaces are pro - vided, as well as a 1-wire ? master and usb, allowing for interconnection to a wide variety of external sensors. a four-input, 10-bit delta-sigma adc monitors analog input from external sensors. the max32625l is a lower-cost version of the max32625, providing 256kb of flash and 128kb of sram. the max32626 is a secure version of the max32625. it incorporates a trust protection unit (tpu) with encryption and advanced security features. these features include a modular arithmetic accelerator (maa) for ecdsa, a hardware prng entropy generator, and a secure boot loader. both the max32626 and the max32625 provide a hardware aes engine. applications sports watches fitness monitors wearable medical patches portable medical devices sensor hubs benefts and features high-efficiency microcontroller for wearable devices ? internal oscillator operates up to 96mhz ? low power 4mhz oscillator system clock option for always-on monitoring applications ? 512kb flash memory (256kb l version) ? 160kb sram (128kb l version) ? 8kb instruction cache ? 1.2v core supply voltage ? 1.8v to 3.3v i/o ? optional 3.3v 5% usb supply voltage ? wide operating temperature: -30c to +85c power management maximizes uptime for battery applications ? 106a/mhz active current executing from cache ? 49a/mhz active current executing from flash ? wake-up to 96mhz clock or 4mhz clock ? 600na low power mode (lp0) current with rtc enabled ? 2.56w ultra-low power data retention sleep mode (lp1) with fast 5s wake-up on 96mhz clock source ? 27a/mhz low power mode (lp2) current optimal peripheral mix provides platform scalability ? spi execute in place (spix) engine for memory expansion with minimal footprint ? three spi masters, one spi slave ? three uarts ? up to two i 2 c masters, one i 2 c slave ? 1-wire master ? full-speed usb 2.0 device with internal transceiver ? sixteen pulse train (pwm) engines ? six 32-bit timers and 3 watchdog timers ? up to 40 general-purpose i/o pins ? 10-bit delta-sigma adc operating at 7.8ksps ? aes -128, -192, -256 ? cmos-level 32khz rtc output available in all power modes secure valuable ip and data with robust internal hardware security (max32626 only) ? trust protection unit (tpu) provides ecdsa and modular arithmetic acceleration support ? prng seed generator ? secure boot loader ordering information appears at end of data sheet. 19-8596; rev 0; 8/16 arm is a registered trademark and registered service mark and cortex is a registered trademark of arm limited. 1-wire is a registered trademark of maxim integrated products, inc. max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables
general description ............................................................................ 1 applications .................................................................................. 1 benefits and features .......................................................................... 1 simplified block diagram ........................................................................ 4 absolute maximum ratings ...................................................................... 5 package information ........................................................................... 5 63 wlp .................................................................................... 5 68 tqfn ................................................................................... 5 electrical characteristics ........................................................................ 6 electrical characteristics - adc ................................................................. 10 electrical characteristics - usb ................................................................... 11 electrical characteristics - spi master / spix master ................................................. 12 electrical characteristics - spi slave ............................................................. 13 electrical characteristics - i 2 c bus ............................................................... 13 pin configurations ............................................................................ 14 pin description ............................................................................... 16 detailed description ........................................................................... 19 max32625/max32626 ....................................................................... 19 arm cortex-m4f processor ................................................................... 19 power operating modes ...................................................................... 19 low power mode 0 (lp0) .................................................................. 19 low power mode 1 (lp1) ................................................................... 19 low power mode 2 (lp2) .................................................................. 19 low power mode 3 (lp3) .................................................................. 19 analog-to-digital converter ................................................................... 19 pulse train engine .......................................................................... 20 clocking scheme ........................................................................... 20 interrupt sources ........................................................................... 21 real-time clock and wake-up timer ........................................................... 21 general-purpose i/o and special function pins ........................................................................ 21 crc module ............................................................................... 21 watchdog timers ........................................................................... 21 programmable timers ........................................................................ 22 serial peripherals ........................................................................... 22 usb ................................................................................... 22 i 2 c master and slave ...................................................................... 23 spi (master) ............................................................................. 23 table of contents maxim integrated 2 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
list of figures list of tables table of contents (continued) spi (slave) .............................................................................. 23 spi (execute in place (spix) master) ......................................................... 23 uart .................................................................................. 23 1-wire master ............................................................................ 24 peripheral management unit (pmu) ............................................................. 24 additional documentation ..................................................................... 24 development and technical support ............................................................ 24 trust protection unit (tpu) (max32626 only) ..................................................... 24 applications information ........................................................................ 25 general-purpose i/o matrix ................................................................... 25 ordering information .......................................................................... 26 revision history .............................................................................. 27 figure 1. spi master and spi xip master timing .................................................... 12 figure 2. max32625/max32626 clock scheme .................................................... 20 figure 3. 32-bit timer ......................................................................... 22 table 1. general-purpose i/o matrix ............................................................. 25 maxim integrated 3 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
simplifed block diagram maxim integrated 4 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
v dd18 ................................................................. -0.3v to +1.89v v dd12 ................................................................. -0.3v to +1.32v v rtc ................................................................... -0.3v to +1.89v v ddb .................................................................... -0.3v to +3.6v v ddio ................................................................... -0.3v to +3.6v v ddioh ................................................................. -0.3v to +3.6v 32kin, 32kout .................................................... -0.3v to +3.6v rstn, srstn, dp, dm, gpio, jtag ................. -0.3v to +3.6v ain[1:0] ................................................................. -0.3v to +5.5v ain[3:2] ................................................................. -0.3v to +3.6v total current into all v ddio and v ddioh power pins combined (sink) ............................................................................ 100ma total current into v ss ...................................................... 100ma output current (sink) by any i/o pin ................................. 25ma output current (source) by any i/o pin ............................ -25ma continuous package power dissipation tqfn (multilayer board) t a = +70c (derate 49.5mw/c above +70c) ...... 3960.4mw operating temperature range ........................... -30c to +85c storage temperature range ............................ -65c to +150c soldering temperature (reflow) ....................................... +260c (all voltages with respect to v ss , unless otherwise noted.) package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packaging . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. 63 wlp package code w6333b+1 outline number 21-100084 land pattern number refer to application note 1891 thermal resistance, single layer board: junction-to-ambient ( ja ) n/a junction-to-case thermal resistance ( jc ) n/a thermal resistance, four layer board: junction-to-ambient ( ja ) 35.87 oc/w junction-to-case thermal resistance ( jc ) n/a 68 tqfn package code t6888+1 outline number 21-0510 land pattern number 90-0354 thermal resistance, single layer board: junction-to-ambient ( ja ) n/a junction-to-case thermal resistance ( jc ) n/a thermal resistance, four layer board: junction-to-ambient ( ja ) 20.20oc/w junction-to-case thermal resistance ( jc ) 1oc/w absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. package information maxim integrated 5 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
(limits are 100% tested at t a = +25oc and t a = +85oc. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. specifications marked gbd are guaranteed by design and not production tested. specifications to -30c are guaranteed by design and are not production tested.) parameter symbol conditions min typ max units power supplies supply voltage v dd18 1.71 1.8 1.89 v v dd12 1.14 1.2 1.26 v rtc 1.75 1.8 1.89 v ddio 1.71 1.8 3.6 v ddioh v ddioh must be v ddio 1.71 1.8 3.6 1.2v internal regulator v reg12 1.14 1.2 1.26 v power-fail reset voltage v rst monitors v dd18 1.61 1.7 v power-on reset voltage v por monitors v dd18 1.5 v ram data retention voltage v drv v dd12 supply, retention in lp1 0.930 mv v dd12 dynamic current, lp3 mode i dd12_dlp3 measured on the v dd12 pin and execut - ing code from cache memory, all inputs are tied to v ss or v dd18 , outputs do not source/sink any current, pmu disabled 106 a/mhz v dd12 fixed current, lp3 mode i dd12_flp3 96mhz oscillator selected as system clock, measured on the v dd12 pin and execut - ing code from cache memory, all inputs are tied to v ss or v dd18 , outputs do not source/sink any current 87 a 4mhz oscillator selected as system clock, measured on the v dd12 pin and execut - ing code from cache memory, all inputs are tied to v ss or v dd18 , outputs do not source/sink any current 39 v dd18 fixed current, lp3 mode i dd18_flp3 96mhz oscillator selected as system clock, measured on the v dd18 pin and execut - ing code from cache memory, all inputs are tied to v ss or v dd18 , outputs do not source/sink any current 366 a 4mhz oscillator selected as system clock, measured on the v dd18 pin and execut - ing code from cache memory, all inputs are tied to v ss or v dd18 , outputs do not source/sink any current 33 v dd12 dynamic current, lp2 mode i dd12_dlp2 measured on the v dd12 pin, arm in sleep mode, pmu with two channels active 27 a/mhz electrical characteristics maxim integrated 6 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
(limits are 100% tested at t a = +25oc and t a = +85oc. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. specifications marked gbd are guaranteed by design and not production tested. specifications to -30c are guaranteed by design and are not production tested.) parameter symbol conditions min typ max units v dd12 fixed current, lp2 mode i dd12_flp2 96mhz oscillator selected as system clock, measured on the v dd12 pin, arm in sleep mode, pmu with two channels active 87 a 4mhz oscillator selected as system clock, measured on the v dd12 pin, arm in sleep mode, pmu with two channels active 39 v dd18 fixed current, lp2 mode i dd18_flp2 96mhz oscillator selected as system clock, measured on the v dd18 pin, arm in sleep mode, pmu with two channels active 366 a 4mhz oscillator selected as system clock, measured on the v dd18 pin, arm in sleep mode, pmu with two channels active 33 v dd12 fixed current, lp1 mode i dd12_flp1 standby state with full data retention 1.06 a v dd18 fixed current, lp1 mode i dd18_flp1 standby state with full data retention 120 na v rtc fixed current, lp1 mode i ddrtc_flp1 rtc enabled, retention regulator powered by v dd12 594 na v dd12 fixed current, lp0 mode i dd12_flp0 14 na v dd18 fixed current, lp0 mode i dd18_flp0 120 na v rtc fixed current, lp0 mode i ddrtc_flp0 rtc enabled 505 na rtc disabled 105 lp2 mode resume time t lp2_on 0 s lp1 mode resume time t lp1_on 5 s lp0 mode resume time t lp0_on polling fash ready 11 s general-purpose i/o input low voltage for all gpio v il_gpio v ddio selected as i/o supply, pin confg - ured as gpio 0.3 v ddio v v ddioh selected as i/o supply, pin confg - ured as gpio 0.3 v ddioh input low voltage for rstn v il_rstn 0.3 x v rtc v input low voltage for srstn v il_srstn 0.3 x v ddio input high voltage for all gpio v ih_gpio v ddio selected as i/o supply, pin confg - ured as gpio 0.7 v ddio v v ih_gpioh v ddioh selected as i/o supply, pin confg - ured as gpio 0.7 v ddioh electrical characteristics (continued) maxim integrated 7 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
(limits are 100% tested at t a = +25oc and t a = +85oc. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. specifications marked gbd are guaranteed by design and not production tested. specifications to -30c are guaranteed by design and are not production tested.) parameter symbol conditions min typ max units input high voltage for rstn v ih_rstn 0.7 x v rtc v input high voltage for srstn v ih_srstn 0.7 x v ddio v output low voltage for all gpio v ol_gpio i ol = 4ma, v ddio = v ddioh = 1.71v, v ddio selected as i/o supply, normal drive confguration, pin confgured as gpio 0.2 0.4 v i ol = 24ma, v ddio = v ddioh = 1.71v, v ddio selected as i/o supply, fast drive confguration, pin confgured as gpio 0.2 0.4 i ol = 900a, v ddio = 1.71v, v ddioh = 2.97v, v ddioh selected as i/o supply, pin confgured as gpio 0.2 0.4 output high voltage for all gpio v oh_gpio i oh = -2ma, v ddio = v ddioh = 1.71v, v ddio selected as i/o supply, normal drive confguration, pin confgured as gpio v ddio - 0.4 v i oh = -8ma, v ddio = v ddioh = 1.71v, v ddio selected as i/o supply, fast drive confguration, pin confgured as gpio v ddio - 0.4 i oh = -900a, v ddioh = 3.6v, v ddioh selected as i/o supply, pin confgured as gpio v ddioh - 0.4 i oh = -2ma, v ddio = 1.71v, v ddioh = 3.6v, v ddio selected as i/o supply, pin confgured as gpio v ddio - 0.50 combined i ol , all gpio i ol_total 48 ma combined i oh , all gpio i oh_total -48 ma input hysteresis (schmitt) v ihys 300 mv input/output pin capacitance for all pins c io 3 pf input leakage current low i il v ddio = 1.89v, v ddioh = 3.6v, v ddioh selected as i/o supply, v in = 0v, internal pullup disabled -100 +100 na input leakage current high i ih v ddio = 1.89v, v ddioh = 3.6v, v ddioh selected as i/o supply, v in = 3.6v, internal pulldown disabled -100 +100 na i off v ddio = 0v, v ddioh = 0v, v ddio selected as i/o supply, v in < 1.89v -1 +1 a i ih3v v ddio = v ddioh = 1.71v, v ddio selected as i/o supply, v in = 3.6v -2 +2 electrical characteristics (continued) maxim integrated 8 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
(limits are 100% tested at t a = +25oc and t a = +85oc. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. specifications marked gbd are guaranteed by design and not production tested. specifications to -30c are guaranteed by design and are not production tested.) parameter symbol conditions min typ max units input pullup resistor to srstn, tms, tck, tdi r pu_vddio pullup to v ddio 25 k input pullup resistor to rstn r pu_vrtc pullup to v rtc 25 k input pullup/pulldown re - sistor for all gpio r pu_norm normal resistance, pin confgured as gpio 25 k r pu_high highest resistance, pin confgured as gpio 1 m jtag input low voltage for tck, tms, tdi v il 0.3 x v ddio v input high voltage for tck, tms, tdi v ih 0.7 x v ddio v output low voltage for tdo v ol 0.2 0.4 v output high voltage for tdo v oh v ddio - 0.4 v clocks system clock frequency f sys_clk 0.001 98 mhz system clock period t sys_clk 1/f sys_ clk ns internal relaxation oscilla - tor frequency f intclk factory default 94 96 98 mhz firmware trimmed, required for usb com - pliance 95.76 96 96.24 internal rc oscillator fre - quency f rcclk 3.9 4 4.1 mhz rtc input frequency f 32kin 32khz watch crystal, 6pf, esr < 70k 32.768 khz rtc operating current i rtc_lp23 lp2 or lp3 mode 0.7 a i rtc_lp01 lp0 or lp1 mode 0.35 rtc power-up time t rtc_ on 250 ms flash memory page size 8 kb flash erase time t m_erase mass erase 30 ms t p_erase page erase 30 flash programming time per word t prog 60 s flash endurance 10 kcycles data retention t ret t a = +25c 10 years electrical characteristics (continued) maxim integrated 9 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
(internal bandgap reference selected and adc_scale = adc_refscl = 1 unless otherwise specified. specifications marked gbd are guaranteed by design and not production tested.) parameter symbol conditions min typ max units resolution 10 bits adc clock rate f adc_clk 0.1 8 mhz adc clock period t adc_clk 1/f adc_ clk s input voltage range v ain ain0-ain3, adc_chsel = 0C3, buf_bypass = 0 0.05 v dd18 v ain0Cain1, adc_chsel = 4C5, buf_bypass = 0 0.05 5.5 ain0Cain3, adc_chsel = 0C3, buf_bypass = 1 v ss v dd18 ain0-ain1, adc_chsel = 4-5, buf_bypass = 1 v ss 5.5 input dynamic current, switched capacitance i ain adc active, adc buffer bypassed 4.5 a adc active, adc buffer enabled 50 na analog input capacitance c ain fixed capacitance to v ss 1 pf dynamically switched capacitance 250 nf integral nonlinearity inl 2 lsb differential nonlinearity dnl 1 lsb offset error v os 1 lsb gain error ge 2 lsb signal-to-noise ratio snr 58.5 db signal-to-noise and distortion sinad 58.5 db total harmonic distortion thd -68.5 db spurious free dynamic range sfdr 74 db adc active current i adc adc active, reference buffer enabled, input buffer disabled 240 a input buffer active current i inbuf 53 a adc setup time t adc_su any power-up of adc clock, adc bias, reference buffer or input buffer, to cpuadcstart 10 s any power-up of adc clock or adc bias to cpuadcstart 48 t aclk adc output latency t adc 1025 taclk adc sample rate f adc 7.8 ksps adc input leakage i adc_leak ain0 or ain1, adc inactive or channel not selected 0.12 4 na ain2 or ain3, adc inactive or channel not selected 0.02 1 electrical characteristics - adc maxim integrated 10 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
(internal bandgap reference selected and adc_scale = adc_refscl = 1 unless otherwise specified. specifications marked gbd are guaranteed by design and not production tested.) (v dd18 = v rst to 1.89v, t a = -30c to +85c.) parameter symbol conditions min typ max units ain0/ain1 resistor divider error adc_chsel = 4 or 5, not including adc offset/gain error 2 lsb full-scale voltage v fs adc code = 0x3ff 1.2 v bandgap temperature coeffcient v tempco box method 30 ppm/c parameter symbol conditions min typ max units usb phy supply voltage v ddb 3.3 v single-ended input high voltage dp, dm v ihd 2 v single-ended input low voltage dp, dm v ild 0.8 v output low voltage dp, dm v old r l = 1.5k from dp to 3.6v 0.3 v output high voltage dp, dm v ohd r l = 15k from dp and dm to v ss 2.8 v differential input sensitivity dp, dm v di dp to dm 0.2 v common-mode voltage range v cm includes v di range 0.8 2.5 v single-ended receiver threshold v se 0.8 2 v single-ended receiver hysteresis v seh 200 mv differential output signal cross-point voltage v crs c l = 50pf, gbd 1.3 2 v dp, dm off-state input impedance r lz 300 k driver output impedance r drv steady-state drive 28 44 dp pull-up resistor r pu idle 0.9 1.575 k dp pullup resistor r pu receiving 1.425 3.09 k usb timing dp, dm rise time (transmit) t r c l = 50pf, gbd 4 20 ns dp, dm fall time (transmit) t f c l = 50pf, gbd 4 20 ns rise/fall time matching (transmit) t r , t f c l = 50pf, gbd 90 110 % electrical characteristics - adc (continued) electrical characteristics - usb maxim integrated 11 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
(timing specifications are guaranteed by design and are not production tested.) figure 1. spi master and spi xip master timing parameter symbol conditions min typ max units master operating frequency f mck 48 mhz master sclk period t mck 1/f mck ns sclk output pulse- width high t mch t mck /2 ns sclk output pulse- width low t mcl (t mck /2) - 4 ns mosi output hold time after sclk sample edge t moh (t mck /2) - 4 ns mosi output valid to sample edge t mov (t mck /2) - 4 ns miso input valid to sclk sample edge setup t mis 1 ns miso input to sclk sample edge t mih 1 ns electrical characteristics - spi master / spix master maxim integrated 12 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
(ac electrical specifications are guaranteed by design and are not production tested, v dd18 = v rst to 1.89v, t a = -30c to +85c.) (limits are 100% tested at t a = +25c and t a = +85c. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. specifications marked "gbd" are guaranteed by design and not production tested.) parameter symbol conditions min typ max units slave operating frequency f sck standard spi mode 22.7 mhz fast spi mode 45.5 sclk period t sck 1/f sck ns parameter symbol conditions min typ max units i 2 c bus input high voltage v ih_i2c standard mode, v ddio selected as i/o supply 0.7 v ddio v standard mode, v ddioh selected as i/o supply 0.7 v ddioh fast mode, v ddio selected as i/o supply 0.7 v ddio v ddio + 0.5 fast mode, v ddioh selected as i/o supply 0.7 v ddioh v ddioh + 0.5 input low voltage v il_i2c standard mode, v ddio selected as i/o supply -0.5 0.3 v ddio v standard mode, v ddioh selected as i/o supply -0.5 0.3 v ddioh fast mode, v ddio selected as i/o supply -0.5 0.3 v ddio fast mode, v ddioh selected as i/o supply -0.5 0.3 v ddioh input hysteresis (schmitt) v ihys_i2c fast mode, v ddio selected as i/o supply 0.05 x v ddio v fast mode, v ddioh selected as i/o supply 0.05 x v ddioh output logic-low (open drain or open collector) v ol_i2c standard mode, i il = 3ma 0 0.4 v fast mode, i il = 3ma 0 0.4 fast mode, i il = 2ma, v ddio selected as i/o supply 0 0.2 x v ddio fast mode, i il = 2ma, v ddioh selected as i/o supply 0 0.2 x v ddioh i 2 c timing scl clock frequency f scl standard mode 0 100 khz fast mode 0 400 electrical characteristics - spi slave electrical characteristics - i 2 c bus maxim integrated 13 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
pin confgurations maxim integrated 14 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
68 tqfn - ep + ep = exposed pad top view max 32625 / max 32626 dp v ddio v ss v ddb p 4 . 5 p 4 . 6 v rtc 32 kout 32 kin dm p 4 . 4 p 4 . 1 p 4 . 2 p 4 . 3 v ddio p 4 . 0 p 3 . 7 45 44 43 42 41 40 39 38 37 36 35 51 50 49 48 47 46 p 2 . 7 p 2 . 6 p 2 . 5 v ss p 2 . 4 p 2 . 3 p 2 . 2 p 2 . 1 p 2 . 0 p 3 . 0 p 3 . 1 p 3 . 5 p 3 . 4 p 3 . 3 p 3 . 2 p 3 . 6 v ss 58 59 60 61 62 63 64 65 66 67 68 52 53 54 55 56 57 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 tck ain 0 tms v dd 18 srstn rstn p 0 . 0 v ddioh p 0 . 1 ain 1 tdo v dd 18 ain 3 tdi ain 2 p 4 . 7 v ss v ddio p 1 . 5 v ss p 1 . 4 p 1 . 3 v dd 12 p 1 . 2 p 1 . 1 p 1 . 0 p 1 . 6 p 1 . 7 p 0 . 7 p 0 . 6 p 0 . 5 p 0 . 4 p 0 . 3 p 0 . 2 28 27 26 25 24 23 22 21 20 19 18 34 33 32 31 30 29 pin confgurations (continued) maxim integrated 15 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
pin name function 63 wlp 68 tqfn power pins a8 23, 32 v dd18 1.8v supply voltage. this pin must be bypassed to v ss with a 1.0f capacitor as close as possible to the package. b8, c8, d1 5, 34, 41, 52, 63 v ss digital ground c1 19, 46 v ddioh i/o supply voltage, high. 1.8v v ddioh 3.6v, always with v ddioh v ddio . see ec table for v ddioh specifcation. this pin must be bypassed to v ss with a 1.0f capacitor as close as possible to the package. c9 37 v rtc rtc supply voltage. this pin must be bypassed to v ss with a 1.0f capacitor as close as possible to the package. d8 3, 42 v ddio i/o supply voltage. 1.8v v ddio 3.6v. see ec table for v ddio specifcation. this pin must be bypassed to v ss with a 1.0f capacitor as close as possible to the package. d9 40 v ddb usb transceiver supply voltage. this pin must be bypassed to v ss with a 1.0f capacitor as close as possible to the package. e1 8 v dd12 1.2v nominal supply voltage. this pin must be bypassed to v ss with a 1.0f capacitor as close as possible to the package. clock pins a9 35 32kin 32khz crystal oscillator input. connect a 6pf 32khz crystal between 32kin and 32kout for rtc operation. optionally, an external clock source can be driven on 32kin if the 32kout pin is left unconnected. a 32khz crystal or external clock source is required for proper usb operation. b9 36 32kout 32khz crystal oscillator output usb pins e8 43 dp usb dp signal. this bidirectional pin carries the positive differential data or single- ended data. this pin is weakly pulled high internally when the usb is disabled. e9 44 dm usb dm signal. this bidirectional pin carries the negative differential data or sin - gle-ended data. this pin is weakly pulled high internally when the usb is disabled. jtag pins b4 26 tck/swclk jtag clock serial wire debug clock this pin has an internal 25k pullup to v ddio . b5 24 tms/swdio/ io jtag test mode select serial wire debug i/o 1-wire master i/o this pin has an internal 25k pullup to v ddio . b6 28 tdo jtag test data output b7 30 tdi jtag test data inputt. this pin has an internal 25k pullup to v ddio . pin description maxim integrated 16 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
pin name function 63 wlp 68 tqfn reset pins a3 22 srstn software reset, active-low input/output. the device remains in software reset while this pin is in its active state. when the pin transitions to its inactive state, the device performs a reset to the arm core, digital registers and peripherals (resetting most of the core logic on the v dd12 supply). this reset does not affect the por only registers, rtc logic, arm debug engine or jtag debugger allowing for a soft reset without having to reconfgure all registers. after the device senses srstn as a logic 0, the pin automatically reconfgures as an output sourcing a logic 0. the device continues to output for 6 system clock cycles and then repeats the input sensing/output driving until srstn is sensed inactive. this pin is internally connected with an internal 25k pullup to the v ddio supply. this pin should be left unconnected if the system design does not provide a reset signal to the device. b3 21 rstn hardware power reset (active-low) input. the device remains in reset while this pin is in its active state. when the pin transitions to its inactive state, the device performs a por reset (resetting all logic on all supplies except for real-time clock circuitry) and begins execution. this pin is internally connected with an internal 25k pullup to the v rtc supply. this pin should be left unconnected if the system design does not provide a reset signal to the device. general-purpose i/o and special functions (see table 1. general-purpose i/o matrix) a2 20 p0.0 gpio port 0.0 b2 18 p0.1 gpio port 0.1 a1 17 p0.2 gpio port 0.2 c4 16 p0.3 gpio port 0.3 c3 15 p0.4 gpio port 0.4 b1 14 p0.5 gpio port 0.5 d4 13 p0.6 gpio port 0.6 c2 12 p0.7 gpio port 0.7 d3 11 p1.0 gpio port 1.0 e4 10 p1.1 gpio port 1.1 d2 9 p1.2 gpio port 1.2 e3 7 p1.3 gpio port 1.3 e2 6 p1.4 gpio port 1.4 f2 4 p1.5 gpio port 1.5 f1 2 p1.6 gpio port 1.6 f3 1 p1.7 gpio port 1.7 g2 67 p2.1 gpio port 2.1 g3 66 p2.2 gpio port 2.2 f4 65 p2.3 gpio port 2.3 g4 64 p2.4 gpio port 2.4 e5 62 p2.5 gpio port 2.5 pin description (continued) maxim integrated 17 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
pin name function 63 wlp 68 tqfn f5 61 p2.6 gpio port 2.6 g5 60 p2.7 gpio port 2.7 e6 59 p3.0 gpio port 3.0 f6 58 p3.1 gpio port 3.1 g6 57 p3.2 gpio port 3.2 d5 56 p3.3 gpio port 3.3 d6 55 p3.4 gpio port 3.4 g7 54 p3.5 gpio port 3.5 f7 53 p3.6 gpio port 3.6 g8 51 p3.7 gpio port 3.7 g9 50 p4.0 gpio port 4.0 e7 49 p4.1 gpio port 4.1 f8 48 p4.2 gpio port 4.2 f9 47 p4.3 gpio port 4.3 d7 45 p4.4 gpio port 4.4 c5 39 p4.5 gpio port 4.5 c6 38 p4.6 gpio port 4.6 c7 33 p4.7 gpio port 4.7 analog input pins a4 25 ain0 adc input 0. 5v tolerant input a5 27 ain1 adc input 1. 5v tolerant input a6 29 ain2 adc input 2 a7 31 ain3 adc input 3 pin description (continued) maxim integrated 18 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
detailed description max32625/max32626 the max32625/max32626 is an ultra-low power, high- efficiency, mixed-signal microcontroller based on the arm cortex-m4f 32-bit core with a maximum operating frequen - cy of 96mhz with a hardware aes engine. an internal 4mhz oscillator supports minimal power consumption for applica - tions requiring always-on monitoring. the max32626 is a secure version of the max32625, incorporating a trust protection unit (tpu) with advanced security features. application code executes from an internal 512kb pro - gram flash memory with up to 160kb sram available for general-application use. an 8kb instruction cache improves execution throughput, and a transparent code scrambling scheme is used to protect customer intellectual property residing in the internal program flash memory. additionally, a spi execute in place (spix) external memory interface allows application code and data (up to 16mb) to be accessed from an external spi memory device. the max32625l is a lower-cost version of the max32625, providing 256kb of flash and 128kb of sram. a 10-bit delta-sigma adc is provided with a multiplexer front end for four external input channels (two of which are 5.5v tolerant) and internal channels to monitor internal voltages. built-in limit monitors allow converted input sam - ples to be compared against user-configurable high and low limits with an option to trigger an interrupt and wake the cpu from a low power mode if attention is required. a wide variety of communications and interface periph - erals are provided. other communications peripherals include a usb 2.0 slave interface, three master spi inter - faces, one slave spi interface, three uart interfaces with multidrop support, up to two master i 2 c interfaces, and one slave i 2 c interface. arm cortex-m4f processor the arm cortex-m4f processor is ideal for the emerging category of wearable medical and wellness applications. the architecture combines high-efficiency signal process - ing functionality with the low power, low cost, and ease- of-use benefits. the arm cortex-m4f dsp supports single instruction multiple data (simd) path dsp extensions, providing: 4 parallel 8-bit add/sub 2 parallel 16-bit add/sub 2 parallel macs 32- or 64-bit accumulate signed, unsigned data with or without saturation power operating modes low power mode 0 (lp0) this mode places the core and peripheral logic in a static, low-power state. all features of the device are disabled except: power sequencer rtc clock (if enabled) key data retention registers power-on reset voltage supply monitoring data retention in this mode can be maintained using only the v rtc supply with all other voltage supplies disabled. low power mode 1 (lp1) this mode places the core logic in a static, low-power state that supports a fast wake-up feature. data retention in this mode can be maintained using only the v rtc sup - ply with all other voltage supplies disabled. low power mode 2 (lp2) this configuration allows the adc and some peripher - als to operate while the arm core is in sleep mode. the peripheral management unit provides intelligent, dynamic clocking of any enabled peripherals, ensuring the lowest possible power consumption. low power mode 3 (lp3) during this state, the cpu is executing application code and all digital and analog peripherals are fully powered and awake. dynamic clocking disables peripherals not in use, providing the optimal mix of high performance and low power consumption. analog-to-digital converter the 10-bit delta-sigma adc provides 4 external inputs and can also measure all internal power supplies. it oper - ates at a maximum of 7.8ksps. ain0 and ain1 are 5v tolerant, making them suitable for monitoring batteries. an optional feature allows samples captured by the adc to be automatically compared against user-programmable high and low limits. up to four channel limit pairs can be configured in this way. the comparison allows the adc to trigger an interrupt (and potentially wake the cpu from a low power sleep mode) when a captured sample goes outside the preprogrammed limit range. since this comparison is performed directly by the sample limit monitors, it can be performed even while the main cpu is suspended in a low power mode. maxim integrated 19 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
the adc measures: ain[3:2] (up to 3.3v) ain[1:0] (up to 5.5v) v dd12 v dd18 v ddb v rtc v ddio v ddioh pulse train engine 16 independent pulse train generators can provide either a square wave or a repeating pattern from 2 bits to 32 bits in length. any single pulse train generator or any desired group of pulse train generators can be synchronized at the bit level allowing for multibit patterns each pulse train generator is independently configurable. the pulse train generators provide the following features: independently enabled multiple pin configurations allow for flexible layout pulse trains can be started/synchronized indepen - dently or as a group frequency of each enabled pulse train generator is also set separately, based on a divide down (divide by 2, divide by 4, divide by 8, and so on) of the input pulse train module clock multiple repetition options for pulse train mode ? single shot (nonrepeating pattern of 2C32 bits) ? pattern repeats user-confgurable number of times or indefnitely ? end of one pulse train's loop count can restart one or more other pulse trains clocking scheme the high-frequency internal relaxation oscillator operates at a nominal frequency of 96mhz. it is the primary clock source for the digital logic and peripherals. select the 4mhz internal oscillator to optimize active power con - sumption. wake-up is possible from either the 4mhz or the 96mhz internal oscillator. an external 32.766khz time base is required when using the rtc or usb features of the device. figure 2. max32625/max32626 clock scheme maxim integrated 20 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
interrupt sources the arm nested vector interrupt controller (nvic) provides high speed, deterministic interrupt response, interrupt masking, and multiple interrupt sources. each peripheral is connected to the nvic and can have multiple interrupt flags indicating the specific source of the interrupt within the peripheral. the nvic provides: up to 43 distinct interrupt sources (including internal and external interrupts) 8 priority levels a dedicated interrupt for each port real-time clock and wake-up timer a real-time clock (rtc) keeps the time of day in absolute seconds. the time base can be generated by connect - ing a 32khz crystal between 32kin and 32kout or an external clock source can be applied to the 32kin pin. the external clock source must meet the electrical/timing requirements in the electrical characteristics table. the 32khz output can be directed on a gpio for observation and use. the 32-bit seconds register can count up to approxi - mately 136 years and be translated to calendar format by application software. a time-of-day alarm and indepen - dent subsecond alarm can cause an interrupt or wake the device from stop mode. the wake-up timer allows the device to remain in low power mode for extended periods of time. the minimum wake-up interval is 244s. general-purpose i/o and special function pins general-purpose i/o (gpio) pins are controlled directly by firmware or one or more peripheral modules connected to that pin. gpio are logically divided into 8-pin ports. each 8-bit port provides a dedicated interrupt. the alternate functions for each pin are shown in table 1 . the following features are independently configurable for each gpio pin: gpio or special function mode operation v ddio or v ddioh supply voltage normal and fast output drive strength open-drain output or high impedance input configurable strong or weak internal pullup/pulldown resistors simple output-only functions ? output from pulse trains (0 through 15) ? output from timers running in 32-bit mode some peripherals have optional pin assignments, allow - ing for greater flexibility during pcb layout. these optional pin assignments are identified with the letter "b," "c," or "d" after the peripheral name. for example, if the "a" con - figuration is chosen for uart0, the uart0_rx signal is mapped to the p0.0 pin. if the "b" configuration is chosen, the uart0_rx signal is mapped to the p0.1 pin. crc module a crc hardware module provides fast calculations and data integrity checks by application software. the crc module supports both the crc-16-ccitt and crc-32 (x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1) polynomials. watchdog timers two independent watchdog timers (wdt0 and wdt1) with window support are provided. the watchdog timers are independent and have multiple clock source options to ensure system security. the watchdog uses a 32-bit timer with prescaler to generate the watchdog reset. when enabled, the watchdog timers must be fed prior to timeout or within a window of time if window mode is enabled. failure to reset the watchdog timer during the programmed timing window results in a watchdog timeout. the wdt0 or wdt1 flags are set on reset if a watchdog expiration caused the system reset. the clock source options for the watchdog timers include: scaled-system clock real-time clock power-management clock a third watchdog timer (wdt2) is provided for recovery from runaway code or system unresponsiveness. when enabled, this watchdog must be reset prior to timeout, resulting in a watchdog timeout. the wdt2 flag is set on reset if a watchdog expiration caused the system reset. wdt2 is unique in that is in the always-on domain, and continues to run even in lp1 or lp0. the timeout period for wdt2 can be programmed as long as 8 seconds. the granularity of the timeout period is intended only for system recovery. maxim integrated 21 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
programmable timers six 32-bit timers provide timing, capture/compare, or gen - eration of pulse-width modulated (pwm) signals. each of the 32-bit timers can also be split into two 16-bit timers, enabling 12 standard 16-bit timers. the 32-bit timer provide a number of features: 32-bit up/down autoreload programmable prescaler pwm output generation capture, compare, and capture/compare capability external input pin for timer input, clock gating or capture, limited to an input frequency of 1/4 of the peripheral clock frequency timer output pin configurable as 2x 16-bit general-purpose timers timer interrupt serial peripherals usb the integrated usb slave controller is compliant with the full-speed (12mb/s) usb 2.0 specification. the integrated usb physical interface (phy) reduces board space and system cost. the usb is powered by the v ddb supply. the usb controller supports dma for the endpoint buf - fers. a total of 7 endpoint buffers are supported with con - figurable selection of in or out in addition to endpoint 0. an external 32khz crystal or clock source is required for usb operation, even if the rtc function is not used. although the usb timing is derived from the internal 96mhz oscillator, the default accuracy is not sufficient for usb operation. periodic firmware adjustments of the 96mhz oscillator, using the 32khz timebase as a reference, are necessary to comply with the usb timing requirements. figure 3. 32-bit timer maxim integrated 22 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
i 2 c master and slave the i 2 c interface is a bidirectional, two-wire serial bus that provides a medium-speed communications network. it can operate as a one-to-one, one-to-many, or many-to- many communications medium. two i 2 c interfaces allow combinations of up to two i 2 c master engines and/or one i 2 c-selectable slave engine to connect to a wide variety of i 2 c-compatible peripherals. these engines support both standard-mode and fast- mode i 2 c standards. the slave engine shares the same i/o port as the master engines and is selected through the i/o configuration settings. it provides the following features: master or slave mode operation supports standard (7-bit) addressing or 10-bit addressing support for clock stretching to allow slower slave devices to operate on higher speed busses multiple transfer rates ? standard mode: 100kbps ? fast mode: 400kbps internal filter to reject noise spikes receiver fifo depth of 16 bytes transmitter fifo depth of 16 bytes spi (master) the spi master-mode-only (spim) interface operates independently in a single or multiple slave system and is fully accessible to the user application. the spi ports provide a highly configurable, flexible, and efficient interface to communicate with a wide variety of spi slave devices. the three spi master ports (spi0, spi1, spi2) support the following features: supports all four spi modes (0, 1, 2, 3) for single-bit communication high-speed ahb access to transmit and receive using 32-byte rx fifo and 16-byte tx fifo 3- or 4-wire mode for single-bit slave device communication full-duplex operation in single-bit, 4-wire mode dual and quad i/o supported up to 5 slave select lines per port up to 2 slave ready lines programmable interface timing programmable sck frequency and duty cycle programmable sck alternate timing ss assertion and deassertion timing with respect to leading/trailing sck edge spi (slave) the spi slave (spis) port provides a highly configurable, flexible, and efficient interface to communicate with a wide variety of spi master devices. the spi slave interface provides the following features: supports spi modes 0 and 3 full-duplex operation in single-bit, 4-wire mode slave select polarity fixed (active low) dual and quad i/o supported high-speed ahb access to transmit and receive using 32-byte fifos four interrupts to monitor fifo levels spi (execute in place (spix) master) the spi execute in place (spix) master allows the cpu to transparently execute instructions stored in an external spi flash. instructions fetched through the spix master are cached just like instructions fetched from internal program memory. the spix master can also be used to access large amounts of external static data that would otherwise reside in internal data memory. uart all three universal asynchronous receiver-transmitter (uart) interfaces support full-duplex asynchronous communication with optional hardware flow control (hfc) modes to prevent data overruns. if hfc mode is enabled on a given port, the system uses two extra pins to implement the industry standard request to send (rts) and clear to send (cts) methodology. each uart is individually programmable. 2-wire interface or 4-wire interface with flow control 32-byte send/receive fifo full-duplex operation for asynchronous data transfers programmable interrupt for receive and transmit independent baud-rate generator programmable 9th bit supports even/odd parity or multi-drop mode user-selectable uart slave address start/stop bit support hardware flow control using rts/cts maximum baud rate: 1843.2 kb maxim integrated 23 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
1-wire master maxim's deepcover ? 1-wire security solutions provide a cost-effective solution to authenticate medical sen - sors and peripherals, preventing counterfeit products. the integrated 1-wire master communicates with slave devices through the bidirectional, multidrop 1-wire bus. all of the devices on the 1-wire bus share one signal that carries data communication and also supplies power to the slave devices. the single contact serial interface is ideal for communication networks requiring minimal inter - connect. features of the 1-wire bus include: single contact for control and operation unique factory identifier for any 1-wire device power is distributed to all slave device (parasitic power) multiple device capability on a single line supports 1-wire standard (15.6 kbps) and overdrive (110 kbps) speeds the incorporation of the 1-wire master enables the creation of 1-wire enhanced consumable and reusable accessories. the following benefits can be added to prod - ucts by the addition of only one contact: oem authenticity is verifiable with sha-256 and ecdsa external tracking is eliminated because calibration data can be securely stored within an accessory reuse of single-use accessories can be prevented counterfeit products can be identified and use denied using the unique, factory identifier environmental temperature and humidity sensing peripheral management unit (pmu) the pmu is a dma-based link list processing engine that performs operations and data transfers involving memory and/or peripherals in the advanced peripheral bus (apb) and advanced high-performance bus (ahb) peripheral memory space while the main cpu is in a sleep state. this allows low-overhead peripheral operations to be performed without the cpu, significantly reducing overall power consumption. using the pmu with the cpu in a sleep state provides a lower-noise environment critical for obtaining optimum adc performance. key features of the pmu engine include: six independent channels with round-robin scheduling allows for multiple parallel operations programmed using pmu opcodes stored in sram pmu action can be initiated from interrupt conditions from peripherals without cpu integrated ahb bus master coprocessor-like state machine additional documentation engineers must have the following documents to fully use this device: this data sheet, containing pin descriptions, feature overviews, and electrical specifications the device-appropriate user guide, containing detailed information and programming guidelines for core features and peripherals errata sheets for specific revisions noting deviations from published specifications visit technical support at support.maximintegrated.com/ micro for more information regarding these documents. development and technical support contact technical support for information about highly versatile, affordable development tools, available from maxim integrated and third-party vendors. evaluation kits software development kit compilers integrated development environments (ides) usb interface modules for programming and debugging visit technical support at support.maximintegrated. com/micro for more information. trust protection unit (tpu) (max32626 only) the tpu enhances cryptographic data security for valu - able intellectual property (ip) and data. a high-speed, dedicated, hardware-based math accelerator (maa) per - forms mathematical computations that support strong cryptographic algorithms including: aes-128 aes-192 aes-256 1024-bit dsa 2048-bit (crt) the device provides a pseudo-random number genera - tor that can be used to create cryptographic keys for any application. a user-selectable entropy source further increases the randomness and key strength. the secure bootloader protects against unauthorized access to program memory. deepcover is a registered trademark of maxim integrated products, inc. maxim integrated 24 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
applications information general-purpose i/o matrix gpio primary function secondary function pulse train output timer input gpio interrupt p0.0 uart0a_rx uart0b_tx pt_pt0 timer_tmr0 gpio_int(p0) p0.1 uart0a_tx uart0b_rx pt_pt1 timer_tmr1 gpio_int(p0) p0.2 uart0a_cts uart0b_rts pt_pt2 timer_tmr2 gpio_int(p0) p0.3 uart0a_rts uart0b_cts pt_pt3 timer_tmr3 gpio_int(p0) p0.4 spim0a_sck pt_pt4 timer_tmr4 gpio_int(p0) p0.5 spim0a_mosi/sdio0 pt_pt5 timer_tmr5 gpio_int(p0) p0.6 spim0a_miso/sdio1 pt_pt6 timer_tmr0 gpio_int(p0) p0.7 spim0a_ss0 pt_pt7 timer_tmr1 gpio_int(p0) p1.0 spim1a_sck spix0a_sck pt_pt8 timer_tmr2 gpio_int(p1) p1.1 spim1a_mosi/sdio0 spix0a_sdio0 pt_pt9 timer_tmr3 gpio_int(p1) p1.2 spim1a_miso/sdio1 spix0a_sdio1 pt_pt10 timer_tmr4 gpio_int(p1) p1.3 spim1a_ss0 spix0a_ss0 pt_pt11 timer_tmr5 gpio_int(p1) p1.4 spim1a_sdio2 spix0a_sdio2 pt_pt12 timer_tmr0 gpio_int(p1) p1.5 spim1a_sdio3 spix0a_sdio3 pt_pt13 timer_tmr1 gpio_int(p1) p1.6 i2cm0a_sda / i2cs0a_sda pt_pt14 timer_tmr2 gpio_int(p1) p1.7 i2cm0a_scl / i2cs0a_scl pt_pt15 timer_tmr3 gpio_int(p1) p2.0 uart1a_rx uart1b_tx pt_pt0 timer_tmr4 gpio_int(p2) p2.1 uart1a_tx uart1b_rx pt_pt1 timer_tmr5 gpio_int(p2) p2.2 uart1a_cts uart1b_rts pt_pt2 timer_tmr0 gpio_int(p2) p2.3 uart1a_rts uart1b_cts pt_pt3 timer_tmr1 gpio_int(p2) p2.4 spim2a_sck pt_pt4 timer_tmr2 gpio_int(p2) p2.5 spim2a_mosi/sdio0 pt_pt5 timer_tmr3 gpio_int(p2) p2.6 spim2a_miso/sdio1 pt_pt6 timer_tmr4 gpio_int(p2) p2.7 spim2a_ss0 pt_pt7 timer_tmr5 gpio_int(p2) p3.0 uart2a_rx uart2b_tx pt_pt8 timer_tmr0 gpio_int(p3) p3.1 uart2a_tx uart2b_rx pt_pt9 timer_tmr1 gpio_int(p3) p3.2 uart2a_cts uart2b_rts pt_pt10 timer_tmr2 gpio_int(p3) p3.3 uart2a_rts uart2b_cts pt_pt11 timer_tmr3 gpio_int(p3) p3.4 i2cm1a_sda / i2cs0b_sda spim2a_ss1 pt_pt12 timer_tmr4 gpio_int(p3) p3.5 i2cm1a_scl / i2cs0b_scl spim2a_ss2 pt_pt13 timer_tmr5 gpio_int(p3) p3.6 spim1a_ss1 spix_ss1 pt_pt14 timer_tmr0 gpio_int(p3) p3.7 spim1a_ss2 spix_ss2 pt_pt15 timer_tmr1 gpio_int(p3) p4.0 owm_i/o spim2a_sr0 pt_pt0 timer_tmr2 gpio_int(p4) p4.1 owm_pupen spim2a_sr1 pt_pt1 timer_tmr3 gpio_int(p4) table 1. general-purpose i/o matrix maxim integrated 25 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
table 1. general-purpose i/o matrix (continued) gpio primary function secondary function pulse train output timer input gpio interrupt p4.2 spim0a_sdio2 spis0a_sdio2 pt_pt2 timer_tmr4 gpio_int(p4) p4.3 spim0a_sdio3 spis0a_sdio3 pt_pt3 timer_tmr5 gpio_int(p4) p4.4 spim0a_ss1 spis0a_sclk pt_pt4 timer_tmr0 gpio_int(p4) p4.5 spim0a_ss2 spis0a_mosi/sdio0 pt_pt5 timer_tmr1 gpio_int(p4) p4.6 spim0a_ss3 spis0a_miso/sdio1 pt_pt6 timer_tmr2 gpio_int(p4) p4.7 spim0a_ss4 spis0a_ss0 pt_pt7 timer_tmr3 gpio_int(p4) + denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. * future productcontact factory for availability. part flash sram trust protection unit (tpu) pin-package max32625iwy+ 512kb 160kb no 63 wlp max32625iwy+t 512kb 160kb no 63 wlp max32625itk+* 512kb 160kb no 68 tqfn max32625itk+t* 512kb 160kb no 68 tqfn max32625iwyl+* 256kb 128kb no 63 wlp max32625iwyl+t* 256kb 128kb no 63 wlp max32625itkl+* 256kb 128kb no 68 tqfn max32625itkl+t* 256kb 128kb no 68 tqfn MAX32626IWY+ 512kb 160kb yes 63 wlp MAX32626IWY+t 512kb 160kb yes 63 wlp max32626itk+* 512kb 160kb yes 68 tqfn max32626itk+t* 512kb 160kb yes 68 tqfn ordering information maxim integrated 26 max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables www.maximintegrated.com
revision number revision date description pages changed 0 8/16 initial release revision history ? 2016 maxim integrated products, inc. 27 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifcations without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max32625/max32626 ultra-low power, high-performance arm cortex-m4f microcontroller for wearables for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.

▲Up To Search▲

Price & Availability of MAX32626IWY

	To Download MAX32626IWY Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .